© C. Laurens-Berge et al., Published by EDP Sciences, 2026

1 Introduction

Polycrystalline silicon (poly-Si) passivating contacts consist of a highly doped poly-Si layer formed on an ultra-thin silicon oxide (SiO_x) interlayer [1]. This structure combines low surface recombination with high carrier selectivity. The SiO_x layer ensures chemical passivation by saturating dangling bonds on the surface of the crystalline silicon (c-Si) substrate. The heavily doped poly-Si layer induces band bending, thus enabling carrier-selective transport and ensuring field-effect passivation. Moreover, the poly-Si layer is located between the metal and the silicon absorber, thereby it suppresses metal-induced recombination.

Conventional tunnel oxide passivated contact (TOPCon) solar cells use a full-area phosphorus-doped poly-Si rear contact in combination with a boron-diffused front emitter [2]. The phosphorus-doped n⁺-poly-Si rear contact has been extensively investigated and demonstrates excellent surface passivation of the silicon wafer while ensuring efficient carrier transport. TOPCon technology was the dominant solar cell technology in 2024, accounting for approximately 57% of the global market share [3]. However, the photovoltaic conversion efficiency of industrial TOPCon solar cells still exhibits a significant gap to the theoretical efficiency limit, underscoring the need for further improvements in surface passivation quality. To fully exploit the potential of poly-Si-based passivated contacts and enable further efficiency gains, new generation device architectures are expected to incorporate double-sided poly-Si contacts, thereby requiring both electron and hole selective poly-Si contacts [4–6] Figure 1a illustrates a solar cell architecture featuring a front-side p⁺-poly-Si contact.

While phosphorus-doped n⁺-poly-Si has shown excellent passivation properties, achieving similarly high-quality passivation with boron-doped p⁺-poly-Si remains challenging [7]. One major limiting factor is boron segregation into the underlying SiO_x layer, which degrades its integrity and reduces chemical passivation effectiveness [7–9]. These issues are further exacerbated on textured silicon surfaces, where oxide uniformity and thermal robustness are more difficult to maintain [10]. In addition, the lower doping level of p⁺-poly-Si constrains the field-effect passivation [11].

The SiO_x layer is a key element of the contact structure, as it must simultaneously withstand high-temperature processing, provide uniform coverage over the textured pyramid surfaces, and remain sufficiently thin to enable efficient carrier tunnelling [7,12,13]. The main reported methods for its formation include thermal oxidation, ozone-based oxidation, plasma-assisted oxidation with N₂O plasma (PANO), UV-assisted oxidation, and chemical oxidation in hot nitric acid. The features of the SiO_x layers have a significant impact on the performances of poly-Si contacts. Previous studies have demonstrated that thicker oxide layers with a composition closer to stoichiometric SiO₂ act as more effective diffusion barriers for dopants, thereby tolerating higher thermal annealing temperatures [14,15]. Moreover, thermally grown SiO_x layers are generally more stoichiometric, provide superior surface passivation properties, and exhibit greater stability during subsequent annealing processes [15,16]. To further improve oxide stability, some studies have explored the combination of different oxidation approaches. For example, Ou et al. reported improved passivation performance by combining thermal oxidation with N₂O plasma-assisted oxidation, leading to reduced interfacial boron accumulation and higher hydrogen concentration compared to PANO oxides [17].

The thickness of the SiO_x layer strongly influences the working principle of carrier transport through the structure. Two distinct transport mechanisms can be identified. When the oxide is thinner than ∼1.6 nm, transport is dominated by tunnelling, whereas for thicknesses exceeding ∼2 nm, conduction is primarily attributed to direct transport (i.e., between the poly-Si and the c-Si absorber) through SiOₓ pinholes formed during high-temperature annealing. An appropriate oxide thickness is also important to ensure effective passivation. Kale et al. have demonstrated that SiO_x layers thinner than 1.4 nm lead to reduced chemical passivation, whereas oxide thicknesses exceeding 1.6 nm result in a degradation of field-effect passivation [18].

This work focuses on optimizing the surface passivation properties of p⁺-poly-Si passivated contacts on textured surfaces. The primary objective was to achieve high passivation quality, targeting a single surface emitter saturation current density (J_0E) of 9 fA·cm⁻² [19] along with good uniformity and reproducibility across samples. In addition, this study aims at understanding the underlying mechanisms that influence passivation quality. To this end, different process strategies were investigated to enhance the J_0E and mitigate degradation effects associated with high-temperature treatments, including variations in tunnel oxide formation, boron diffusion temperature, and poly-Si layer thickness.

Fig. 1 (a) Schematic cross-sectional view of a TOPCon solar cell featuring front-side p⁺-poly-Si contacts; (b) schematic illustration of the BCl3 diffusion temperature profile for drive-in temperatures of 850 °C, 900 °C, and 950 °C; (c) schematic cross-sectional view of the symmetrical samples investigated in this study.

2 Material and methods

2.1 Preparation of symmetrical p-poly-Si contacts

Symmetrical test structures were fabricated on textured n-type Czochralski crystalline silicon (c-Si) wafers, with an area of 156 × 156 mm², a thickness of 170 μm and a resistivity of 2 Ω.cm. The wafers were textured in an alkaline solution containing additives, leading to pyramids whose size ranges from 1.3 μm to 1.8 μm. The fabrication sequence began with a standard RCA cleaning process, followed by the formation of ultra-thin oxides on the wafer surfaces. Two oxide configurations were investigated: a thermal oxide (TO) and a hybrid oxide consisting of an O₃-based chemical oxide formed by an ozonized DI-H₂O rinsing followed by thermal oxidation (O₃+TO). The thermal oxidation was performed in situ in a low-pressure chemical vapor deposition (LPCVD) furnace at 630 °C, with varied oxidation times. Subsequently, an intrinsic polycrystalline silicon (i-poly-Si) layer was deposited at 630 °C under a pressure of 180 mTorr. The deposition temperature and pressure were kept constant throughout all studies. Under these conditions, the deposition rate was estimated to be approximately 10 nm·min⁻¹ on polished wafers. For textured wafers, an effective growth rate of ∼6.25 nm·min⁻¹ was considered. This correction accounts for the increased surface area of the textured silicon surface. Boron doping of the poly-Si layer was then carried out in a diffusion furnace using BCl₃ as the dopant source. Figure 1b illustrates a typical BCl₃ diffusion recipe, which consists of two distinct stages. First, a BSG layer is formed through the so-called deposition step, during which at 850 °C the diffusion tube is supplied with O₂ and BCl₃ diluted in N₂. Second, a drive-in step is performed under N₂ ambient allowing boron diffusion from the BSG into the poly-Si layer and the underlying c-Si. The amount of incorporated boron and the resulting doping profiles are primarily controlled by the drive-in temperature and duration. Here, the drive-in temperature was varied between 850 °C and 950 °C, with a constant duration of 30 min. The borosilicate glass (BSG) formed on the sample surface was removed by etching in a hydrofluoric acid (HF) solution.

Subsequently, a hydrogenation step based on the deposition of H-rich dielectric layers was performed to passivate silicon dangling bonds at the c-Si/SiO_x interface [11,20,21]. To this end, two different layer structures were used. The main structure consists of a single 45 nm-thick hydrogenated silicon nitride (SiN_x:H) layer deposited by plasma-enhanced chemical vapor deposition (PECVD) at 450 °C. In part 3.4, a stack composed of a 10 nm-thick hydrogenated aluminium oxide (AlO_x:H) layer deposited on both sample surfaces at 200 °C by atomic layer deposition (ALD), capped with a 45nm-thick SiN_x:H layer was used instead. For both configurations, a firing step with a peak temperature of 790 °C was applied to activate hydrogen diffusion into the underlying materials. A schematic representation of the sample structure is provided in Figure 1c.

2.2 Characterizations

The carrier recombination properties were assessed by inductively-coupled photo-conductance decay (IC-PCD) measurements using a Sinton WCT-120 instrument [22]. The J_0E and the implied open-circuit voltage (iV_OC) were extracted to evaluate the surface passivation. The J_0E was extracted from the PCD measurements using the Kane and Swanson method [23]. The iV_OC at one sun was calculated as follows:

$$i{V}_{OC}= \frac{kT}{q}\ln \left(\frac{\Delta n\left(\Delta n+n_0\right)}{n_i^2}\right)$$(1)

where k is the Boltzmann constant, T is the temperature, q is the elementary charge, Δn is the excess carrier density, n₀ is the equilibrium majority carrier density and n_i is the intrinsic carrier density.

IC-PCD measurements were performed in the center of each sample. In addition, Photoluminescence (PL) images were acquired with a LIS-R2 (BT Imaging) equipment to assess the spatial homogeneity of the passivation [24]. All measurements were conducted under identical conditions, and the PL images are presented using the same intensity scales unless otherwise specified. The hole density profile (corresponding to the electrically active boron doping profile) of the poly-Si layer was measured by electrochemical-capacitance-voltage (ECV) measurements on KOH-polished wafers using a WEP Wafer Profiler CVP2 with a 0.1 mol/L NH₄F solution as etchant. The hole density profiles were then analyzed using EDNA 2, a simulation tool from PVlighthouse [25], to calculate the Auger saturation current density J_0E,Auger due to the shallow boron-diffused region of the c-Si beneath the doped poly-Si contact. Furthermore, the J_0E extracted from PCD measurements was compared with the J_0E,Auger obtained from EDNA 2 simulations.

Spectroscopic ellipsometry (SE) measurements were performed using a UVISEL ellipsometer (HORIBA Jobin Yvon S.A.S.). The acquired spectra were analyzed using the DeltaPsi2 software. Both i-poly-Si/SiO_x and p⁺-poly-Si/SiO_x structures were characterized on chemically polished wafers (35% KOH solution). For the fitting model of the intrinsic and doped poly-Si layers, a Bruggeman effective medium approximation was used with a mixture of small and large grains. The optical constants for the large and small grain materials were taken from [26]. The thickness values obtained from the fitting model are divided by 1.6 to estimate the corresponding thicknesses on textured wafers, reflecting the surface area increase induced by texturing. In addition, the imaginary part of the pseudo-dielectric function (ε_i) analyzed as a function of photon energy (E_ph) provides qualitative insights into the material microstructure.

SE was also used to measure the oxide thicknesses on (100) chemical mechanical polishing (CMP) wafers. The time interval between wafer cleaning with or without a final ozonized DI-H₂O rinsing, thermal oxidation in the LPCVD tube, and SE measurements was minimized to limit any native oxide regrowth. For all the “oxide samples”, a model for native oxide was used to allow for a qualitative comparison.

3 Oxide tunnel tuning and optimization of the BCl₃ drive-in temperature

In this section, different tunnel oxide configurations and BCl₃ drive-in temperatures were investigated. Three samples were prepared for each condition.

3.1 Measurements of SiO_x thickness using spectroscopic ellipsometry

Six oxide conditions were studied, including thermal oxides and combined oxides with O₃-based and thermal oxidations. Three thermal oxidations were studied: 10 min, 20 min and 30 min. The oxide thicknesses evaluated through SE measurements on CMP samples are displayed in Table 1.

Only the TO10’ sample exhibited an oxide thickness below 1.6 nm. These measurements were performed on wafers with a (100) surface orientation, while textured wafers predominantly expose (111) facets. For ultra-thin SiO_x layers (< 2 nm), thermal oxidation on (111) surfaces is expected to be slightly reduced compared to (100) surfaces [27]. A more accurate determination of the SiO_x thickness would require high-resolution transmission electron microscopy (HR-TEM). Previous studies have reported that spectroscopic ellipsometry (SE) may overestimate the oxide thickness by approximately 0.3 nm relative to TEM measurements [27]. This overestimation is likely associated with the presence of organic residues adsorbed on the surface between processing steps, which can affect the optical response measured by SE.

In addition, the reported oxide thicknesses were evaluated immediately after the thermal oxidation step. However, during the formation of the p⁺-poly-Si contacts, the oxides subsequently undergo high-temperature processing through the BCl₃ diffusion and during the firing step, reaching maximum temperatures of approximately 950 °C and 790 °C, respectively. Polzin et al. noticed an increase of 0.3 nm in thermal oxide thickness after annealing at 900 °C [14], whereas Varghese et al. observed no significant change in oxide thickness during high-temperature processing, including i-poly-Si deposition and ex-situ boron diffusion [27].

The oxide thicknesses obtained in this study are expected to remain around or below 1.6 nm, indicating that all the tested oxides should allow an efficient carrier transport via tunnelling. Further studies will be launched to confirm this hypothesis, based on dark current–voltage (I–V) measurements to assess the contact resistivity (ρ_c) of the poly-Si/c-Si interface [28].

3.2 Impact on passivation properties of p⁺-poly-Si layer

Following the oxide formation, the i-poly-Si deposition time was set to 8 min, corresponding to thicknesses of 80 nm on polished surfaces (about 50 nm on textured surfaces). The p⁺-poly-Si layers were doped using a BCl₃ diffusion with three drive-in temperatures: 850 °C, 900 °C and 950 °C. After BSG removal, the p⁺-poly-Si thicknesses and large-grain fractions were obtained from SE measurements (KOH-polished samples) and are reported in Table 2. The reported thickness values of poly-Si layers were corrected by a factor of 1.6 to account for the textured surface morphology.

Following boron diffusion, a reduction in the poly-Si thickness is expected due to the combined effects of high-temperature-induced densification and poly-Si consumption to form the borosilicate glass (BSG) layer, which is subsequently removed during BSG etching. Table 2 shows that the p⁺-poly-Si thickness decreases with increasing the BCl₃ diffusion drive-in temperature. Since the BSG deposition step was done the same way for all samples (only the drive-in temperature was varied), this suggests that the poly-Si consumption associated with the BSG formation remains unchanged. Therefore, the observed thickness reduction is mainly attributed to enhanced densification at higher drive-in temperatures. Moreover, the fraction of large grains relative to small grains increases with increasing drive-in temperature.

A SiN_x:H single-layer was deposited on both surfaces to provide hydrogen at the SiO_x/c-Si interface. It is worth noticing that an internal study (not presented here) showed that a SiN_x:H single layer yields post-firing J_0E values comparable to those obtained with an AlO_x/SiN_x:H stack for a given symmetrical p⁺-poly-Si structure.

Figure 2 shows the impact of the tunnel oxide formation conditions and of the drive-in temperature on the J_0E, iV_OC and the PL images after firing (textured samples).

PL images along with J_0E and iV_OC values measured at the wafer center, indicate that the defectivity pattern disappears when an O₃-based oxide is introduced prior to thermal oxidation. A drive-in temperature of 950 °C results in the lowest level of surface passivation, particularly for less robust oxides (i.e. without O₃ and 10 min-long thermal oxidation). The O₃+TO20^′ condition combined with a drive-in temperature of 850 °C yields the lowest mean J_0E value of 25.6 fA·cm⁻² (mean iV_OC of 701.6 mV).

The defectivity pattern exhibits a donut-like shape and is observed on both polished and textured wafers. It is attributed to the limited robustness of the thermally grown tunnel oxide, which, when formed without combination with an O₃-based oxide, is insufficiently stable to withstand high-temperature processing. The defect pattern observed for the TO20^′ condition is less pronounced than that for TO30^′. This trend is unexpected since a longer thermal oxidation should produce a more robust oxide and consequently, a less pronounced defect pattern.

The PL images of the O₃+TO20^′ and O₃+TO30^′ conditions with a drive-in temperature of 950 °C exhibit swirl-shaped regions. Such swirl patterns are typically associated with bulk defects (e.g., silicon oxide precipitates) originating from the Czochralski (Cz) crystal growth process.

It can be noted that the PL images show limited homogeneity, with localized low-PL regions that may be attributed to sample handling and surface scratches.

Fig. 2 For the different processing conditions: (a) J0E and iVOC measured after firing and (b) corresponding PL images acquired after firing of the complete symmetrical structures (textured samples).

3.3 ECV and J_0E,Auger

In this section, the hole concentration (assumed to be equal to the electrically active boron concentration) profiles obtained by ECV are presented for different process parameters. Figure 3a shows profiles for various oxide conditions at a fixed BCl₃ drive-in temperature of 900 °C, while Figure 3b shows profiles for a fixed oxide configuration (O₃ + TO30^′) and varying BCl₃ drive-in temperatures. Table 3 summarizes the contribution of J_0E,Auger calculated using EDNA 2 from the ECV profiles of Figure 3, to the J_0E extracted from PCD measurements (see Fig. 2a).

The ECV profiles show a steep hole concentration drop at the SiO_x/c-Si interface demonstrating the dopant-blocking capability of the SiO_x layer. According to the ECV profiles, the p⁺-poly-Si layer has a thickness of approximately 65 nm on polished wafers, indicating partial consumption of the initial 80 nm intrinsic poly-Si layer during BCl₃ diffusion and subsequent borosilicate glass (BSG) removal. This value is in good agreement with spectroscopic ellipsometry measurements, which also yield a thickness of approximately 65 nm.

Figure 3a shows that O₃-based oxides allow to slightly reduce the boron penetration into the c-Si substrate. As a result, Auger recombination is slightly reduced, as indicated in Table 3a. A longer thermal oxidation is expected to produce a denser SiO_x layer, likely to hinder boron diffusion into the c-Si substrate which would result in a shallower dopant profile. However, such a behavior is not observed with O₃ combinations. Furthermore, the electrically active boron concentration within the poly-Si layer shows only minor variations among the different oxide conditions without any discernible trend. For all oxide configurations, the ECV profiles show a gradual increase in the electrically active boron concentration with depth across the poly-Si layer. The boron concentration at the poly-Si/SiO_x interface ranges between 7.3 × 10¹⁹ cm⁻³ and 8.3 × 10¹⁹ cm⁻³ which is in good agreement with the boron solubility limit in c-Si at 900 °C (about 1 × 10²⁰ cm⁻³) [29].

Figure 3b shows that increasing the boron diffusion drive-in temperature results in deeper boron diffusion into the c-Si substrate. This trend is also reflected by the J_0E,Auger values. Table 3b shows that increasing the drive-in temperature leads to higher J_0E,Auger values, along with an increased relative contribution of Auger recombination. However, the boron concentration in the p⁺-poly-Si layer remains similar for drive-in temperatures of 850 °C, 900 °C, and 950 °C, suggesting that a saturation level is reached.

Table 3 shows that Auger recombination features limited contributions to the emitter recombination losses (therefore essentially due to Shockley-Read-Hall surface recombination). It should be noted that the ECV measurements were carried out on KOH-polished wafers, as this approach provides the most reliable determination of the boron doping profiles. Consequently, the obtained boron distributions are expected to differ from those on textured surfaces due to variations in the poly-Si and interfacial SiO_x thicknesses. However, these variations are not expected to alter the main conclusions drawn from this study.

In addition, ECV measurements provide the concentration of electrically active boron only. For a more comprehensive assessment of the total boron concentration distribution, secondary ion mass spectrometry (SIMS) measurements should be performed.

Fig. 3 ECV profiles on KOH-polished samples: (a) variation of the oxide condition for a BCl3 diffusion drive-in temperature of 900 °C; (b) variation of the BCl3 diffusion drive-in temperature for a fixed oxide configuration (O3+TO30′).

3.4 Pattern identification

In Section 3.2, a pronounced degradation of the J_0E is observed at the center of some wafers, due to a concentric defectivity pattern observable through PL images both before and after firing. This defective pattern appears for conditions with only thermal oxides. As seen in Figure 2b, for these conditions, the samples seem more impacted by the thermal budget of the boron diffusion.

To identify the origin of this defectivity pattern, the contribution of each high-temperature process step was first separately assessed. The LPCVD deposition, the boron diffusion and the firing temperature involve high temperatures (630 °C, 850 °C to 950 °C and 790 °C, respectively) and may affect the surface and bulk carrier recombination properties. To decouple the effect of the LPCVD deposition and the boron diffusion, two types of reference samples were fabricated: i) intrinsic poly-Si layers without subsequent boron diffusion ii) boron emitters processed without poly-Si deposition. For hydrogenation, a SiN_x:H/AlO_x:H stack was deposited, followed by a firing step. Figures 4a and 4b present the corresponding PL images and the associated iV_OC values. No PL defectivity patterns were observed after either the LPCVD process or the BCl₃ diffusion alone. In addition, PCD measurements indicate that the i-poly-Si samples exhibit excellent surface passivation, with J_0E values reaching 22 fA cm⁻², reflecting strong chemical passivation. For the p⁺-emitter samples, J_0E values of approximately 27 fA·cm⁻² are obtained, demonstrating effective field-effect passivation and indicating that the bulk c-Si is not degraded (at least not significantly) by the boron diffusion process alone.

The defectivity pattern appears only when both steps are combined, suggesting that the BCl₃ diffusion step degrades the previously formed poly-Si contact. To clarify whether this degradation is thermally induced or specifically related to boron incorporation, additional experiments were conducted. Symmetrical intrinsic poly-Si samples were subjected to a high-temperature thermal treatment at 950 °C, replicating the thermal budget of the boron diffusion step, followed by AlO_x/SiN_x deposition and a firing step. Figure 4c shows the corresponding PL images. The passivation quality was insufficient to extract J_0E values. PL images obtained after firing reveal the appearance of a similar defectivity pattern, which is even more pronounced likely due to the absence of field-effect passivation compensation. This observation indicates that the degradation is rather thermally-induced than boron-related.

Based on the above findings, a particular attention must be paid to the thermal stability of the poly-Si contact during high-temperature processing. The defectivity pattern is likely associated with local degradations of the SiO_x layer under elevated thermal budgets. Improving the robustness of the oxide and optimizing the applied high-temperature processing steps are critical to achieve high, homogeneous and reproducible passivation levels.

Fig. 4 Different processing conditions, their corresponding schematic cross-sectional views, and the resulting passivation performance, including iVOC measured at the wafer center and the corresponding PL images: (a) i-poly after firing, (b) BCl3 diffused emitter without poly-Si after firing, (c) i-poly-Si sample subjected to a BCl3-deprived thermal treatment at 950 °C after firing.

4 Optimization of the poly-Si thickness

In this section, the effect of the poly-Si layer thickness was investigated. Four different thicknesses were tested by adjusting the intrinsic poly-Si deposition time to 8 min, 12 min, 15 min, and 19 min. The corresponding thicknesses were measured by SE on KOH-polished samples. After correction for textured surfaces, the measured thicknesses were 54 nm, 81 nm, 97 nm, and 124 nm, respectively.

A BCl₃ diffusion was performed with a drive-in temperature of 900 °C. Following boron diffusion, a reduction in the poly-Si thickness is expected. After BSG removal, the p⁺-poly-Si thickness obtained on textured surfaces could be extrapolated from SE measurements on KOH-polished samples to 41 nm, 65 nm, 82 nm, and 108 nm, respectively. Overall, a thickness reduction close to 16 nm was observed for each condition through BCl₃ diffusion /BSG removal.

After p⁺-poly-Si contact formation, hydrogenation was provided by single SiN_x:H layers deposited by PECVD, before a firing step.

Figures 5a, 5b and 5c present the J_0E and iV_OC measurements and the corresponding PL images after firing, respectively (textured samples). Figure 5d shows the ECV profiles of the p^⁺-poly-Si layers (KOH-polished samples). Moreover, Table 4 summarizes the contribution of J_0E,Auger calculated using EDNA 2, to the J_0E extracted from PCD measurements. In addition, the microstructure of the intrinsic and doped poly-Si layers (KOH-polished samples) was evaluated using SE by analysing the imaginary part of the dielectric function (ε_i) as a function of photon energy (E_ph), as shown in Figures 5e and 5f.

Figures 5a, 5b and 5c show that before firing slight differences in J_0E and iV_OC are observed among the different i-poly-Si deposition times. After firing, the J_0E values remain close to 20 fA.cm⁻² across the investigated range of i-poly-Si deposition times, with homogeneous photoluminescence (PL) images observed for all samples. The J_0E improvement after firing, combined with uniform photoluminescence across the investigated poly-Si thicknesses, highlights the important role of hydrogenation in achieving high quality surface passivation. In addition, Table 4 indicates that the contribution of Auger recombination is still limited, ranging from 14.8% and 21.1%.

It can be noticed that higher J_0E values are observed after firing compared to those reported in part 5, despite using the same wafers. This difference can be attributed to slight process variations that may occur between runs, which can impact the final passivation quality.

In addition, the PL images exhibit limited spatial homogeneity, with localized regions of reduced luminescence. These features are likely related to handling-induced scratches, which locally increase the recombination activity.

As shown in Figure 5d, the electrically active boron concentration within the poly-Si layer is the highest for the shortest deposition time of 8 min. The poly-Si thickness appears to have only a minor influence on the electrically active boron concentration in the poly-Si, as the concentration measured for the 19 min-long deposition lies between those obtained for the 15 min-long and 8 min-long depositions.

The SE curves in Figure 5e exhibit the characteristic features associated with the polycrystalline phase. Hydrogenated amorphous silicon (a-Si:H) exhibits a single broad peak centered at approximately 3.5 eV, whereas c-Si shows two distinct peaks near 3.4 eV and 4.2 eV. Materials with intermediate crystallinity, such as microcrystalline silicon (μc-Si), display a spectral response between these two limits [30]. The LPCVD deposition was performed at 630 °C, for which films are reported to be predominantly polycrystalline rather than amorphous [31]. Figure 5f shows that the crystallinity is enhanced after the diffusion steps, with the two-peaks feature characteristic of the polycrystalline phase becoming more clearly distinguishable.

Fig. 5 For the different poly-Si deposition times: (a) and (b) J0E and iVOC measured before and after firing; (c) corresponding PL images acquired after firing; (d) ECV profiles of the p+-poly-Si layers; (e) SE results showing the imaginary part of the dielectric function (εᵢ) as a function of photon energy (Eph) for intrinsic poly-Si symmetrical samples; and (f) comparison of εi(Eph) between intrinsic and p⁺-poly-Si layers for a 8 min deposition time.

5 Conclusion and outlook

In this work, the mechanisms driving the surface passivation of boron-doped p⁺-poly-Si contacts on textured surfaces were studied and their performances improved.

Thermal oxides, as well as combined oxide stacks consisting of O₃-based and thermally grown SiO_x layers, were investigated. SE results indicate that the investigated oxides are sufficiently thin (<2 nm) to enable carrier transport via tunnelling. The oxide thickness is a key parameter to achieve effective surface passivation of c-Si while maintaining low resistance for majority carrier transport.

In terms of passivation performance, the combination of O₃-based and thermally grown oxides significantly reduces the J_0E and effectively suppresses the defect-related patterns observed in the PL images. Moreover, the boron diffusion drive-in temperature strongly influences the thermal stability of the SiO_x layer, particularly for less robust oxides. An optimal drive-in temperature between 850 °C and 900 °C was identified, providing the highest surface passivation levels. As a result, improved and more uniform surface passivation levels were achieved, with J_0E between 26.2 and 28.6 fA.cm⁻² for samples incorporating a combined O₃-based and thermal oxidation.

Experimental investigations revealed that the observed defectivity pattern does not originate from a single processing step, but rather from the combined interactions between the LPCVD poly-Si deposition and the subsequent BCl₃ diffusion. Moreover, the BCl₃ diffusion process does not degrade the silicon bulk, the degradation is confined to the poly-Si contact. Furthermore, this degradation pattern would originate from temperature-induced degradation of the interfacial SiO_x during the boron diffusion process, and would not be caused by diffusion or accumulation effects of the boron atoms.

In addition, comparable passivation performances are observed over the investigated range of p⁺-poly-Si thicknesses (from approximatively 41 nm to 108 nm) for samples processed with combined O₃ and thermal oxides and a boron diffusion drive-in temperature of 900 °C. Further studies will focus on reducing the poly-Si layer thickness. Indeed, when implemented on the front side, doped poly-Si layers introduce parasitic optical absorptions, which can significantly reduce the short circuit current density (J_SC) [32]. Therefore, minimizing the poly-Si thickness is critical to mitigate absorption losses while preserving adequate surface passivation and carrier selectivity.

Future work will focus on further improving the performance and thermal stability of p⁺-poly-Si passivating contacts. A pre-annealing step will be investigated to promote poly-Si grain growth and enhance film crystallinity [33]. In addition, multilayer poly-Si configurations will be explored as a strategy to limit boron segregation at the SiO_x interface [19]. Eventually, optimization of the surface texturing, particularly through the rounding of pyramid edges, will be considered to reduce local disruptions of the SiOₓ interlayer and improve oxide robustness [34].

Acknowledgments

The authors gratefully acknowledge the French Environment and Energy Management Agency (ADEME) for its financial support of the PV ENLIGHT project.

Funding

This research received no external funding.

Conflicts of interest

The authors have nothing to disclose.

Data availability statement

Reported data can be provided upon request.

Author contribution statement

C. Laurens-Berge: Conceptualization, Methodology, Formal Analysis, Investigation, Data curation, Writing – Original Draft, Writing- Review Preparation & Editing. R. Cabal and S. Dubois: Conceptualization, Methodology, Supervision, Writing – review & editing, Funding acquisition, Project Administration.

References

All Tables

All Figures

	Fig. 1 (a) Schematic cross-sectional view of a TOPCon solar cell featuring front-side p⁺-poly-Si contacts; (b) schematic illustration of the BCl3 diffusion temperature profile for drive-in temperatures of 850 °C, 900 °C, and 950 °C; (c) schematic cross-sectional view of the symmetrical samples investigated in this study.
In the text

	Fig. 2 For the different processing conditions: (a) J0E and iVOC measured after firing and (b) corresponding PL images acquired after firing of the complete symmetrical structures (textured samples).
In the text

	Fig. 3 ECV profiles on KOH-polished samples: (a) variation of the oxide condition for a BCl3 diffusion drive-in temperature of 900 °C; (b) variation of the BCl3 diffusion drive-in temperature for a fixed oxide configuration (O3+TO30′).
In the text

	Fig. 4 Different processing conditions, their corresponding schematic cross-sectional views, and the resulting passivation performance, including iVOC measured at the wafer center and the corresponding PL images: (a) i-poly after firing, (b) BCl3 diffused emitter without poly-Si after firing, (c) i-poly-Si sample subjected to a BCl3-deprived thermal treatment at 950 °C after firing.
In the text

Fig. 5 For the different poly-Si deposition times: (a) and (b) J0E and iVOC measured before and after firing; (c) corresponding PL images acquired after firing; (d) ECV profiles of the p+-poly-Si layers; (e) SE results showing the imaginary part of the dielectric function (εᵢ) as a function of photon energy (Eph) for intrinsic poly-Si symmetrical samples; and (f) comparison of εi(Eph) between intrinsic and p⁺-poly-Si layers for a 8 min deposition time.

In the text