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Table 4
Summary of simulated abnormal performance scenarios.
| Scenario | Description |
|---|---|
| Default | Default losses are applied. This is an array that performs exactly as expected with expected module and system losses. |
| Perfect | The array performs perfectly according to nameplate values without balance of system losses (wiring, mismatch, resistance, soiling). |
| 1 string fail | The number of strings is reduced by 1. |
| 1 module fail | The number of modules per string is reduced by 1. |
| 2 module fail | The number of modules per string is reduced by 2. |
| Derated inverter | Inverter AC output is reduced by 5%. |
| Overclipping 5% | The inverter output is curtailed at PAC,0 × 0.95. |
| Overclipping 10% | The inverter output is curtailed at PAC,0 × 0.90. |
| 5% more soiling | Soiling loss is increased from 2% to 7%. |
| Mismatch | Mismatch loss is increased from 1% to 6%. |
| Wiring 1 | DC resistance loss is increased from 1% to 15% at Pout,k = P0. |
| Wiring 2 | DC resistance loss is increased from 1% to 60% at Pout,k = P0. |
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