Impact of PECVD mc-Si:H deposition on tunnel oxide for passivating contacts

Passivating contacts are becoming amainstream option in current photovoltaic industry due to their ability to provide an outstanding surface passivation along with a good conductivity for carrier collection. However, their integration usually requires long annealing steps which are not desirable in industry. In this work we study PECVD as a way to carry out all deposition steps: silicon oxide (SiOx), doped polycrystalline silicon (poly-Si) and silicon nitride (SiNx:H), followed by a single firing step. Blistering of the poly-Si layer has been avoided by depositing (p) microcrystalline silicon (mc-Si:H). We report on the impact of this deposition step on the SiOx layer deposited by PECVD, and on the passivation properties by comparing PECVD and wet-chemical oxide in this hole-selective passivating contact stack. We have reached iVoc > 690mV on p-type FZ wafers for wet-chemical SiOx\(p ) mc-Si\SiNx:H with no annealing step.


Introduction
Crystalline silicon solar cell is the dominant technology in today's photovoltaic (PV) market. In order to foster PV development and make it economically more competitive, it is necessary to further reduce production costs as well as to increase cell efficiencies. In order to achieve the latter, reducing recombination losses at the metal/semiconductor interface is of paramount importance. To do so, the integration of so-called passivating contacts is a mainstream option [1][2][3]: they consist of a silicon oxide (SiO x )\ doped polycrystalline silicon (poly-Si) stack that allows an outstanding surface passivation while providing a low series resistance and higher conductivity than doped a-Si:H.
As for cost reduction, the main option is to reduce the number of processing steps. For example, Ingenito et al. use a single firing step to both contact and anneal the cell, while limiting the overall thermal budget applied to the silicon wafer [4]. Additionally, SiO x and doped poly-Si layers can be deposited sequentially by PECVD [5].
Another way to further reduce costs is to use low-cost, high quality silicon wafers. This is the case of the castmono silicon technology, which has reached industrial maturity and is currently being commercialized by companies such as Photowatt through their technology Crystal Advanced [6].
The aim of this work is to study the feasibility of a low thermal budget-route for hole-selective passivating contacts fabrication using a full PECVD process, and to investigate the relevance of using mono-cast silicon wafers. Firstly the SiO x and (p + ) poly-Si layers were developed on one side of double side polished (DSP) n-type Cz silicon wafers (280 mm thick, and wafer resistivity of 1-5 V.cm), that were cleaned with a HF dip (5% for 30 s). Secondly, the "lifetime samples" were symmetrical structures, deposited on three kinds of p-type silicon substrates described in Table 1.
These wafers were RCA cleaned and the remaining oxide was removed by an HF dip (HF 5% diluted in deionized water DIW, for 20 s).

Tools
The SiO x layer was either deposited in an RF-PECVD reactor Octopus II (INDEOtec) at 175°C with a gas mixture of SiH 4 , H 2 and CO 2 , or wet-chemically grown using a second round of RCA2 process (DIW, H 2 O 2 , HCl mixture for 10 min at 75°C). The (p + ) Si layer was deposited by PECVD in Octopus II at 175°C with a gas mixture of SiH 4 , H 2 and trimethylborane (B(CH 3 ) 3 , noted TMB). The silicon nitride layer (SiN x :H) was deposited in a capacitively coupled RF-PECVD reactor (MVSystems) at 340°C with a gas mixture of SiH 4 and NH 3 . On a few symmetric samples we deposited a stack of (i) a-Si:H\(n + ) a-Si:H in Octopus II at 175°C. The annealing and firing steps were done in a Jetfirst rapid thermal annealing furnace (Jipelec).

Different batches
In Batch 1, as-deposited 1-2 nm thick PECVD SiO x , as well as the 30 nm thick PECVD (p + ) mc-Si:H on SiO x before and after firing step (1 s at 850°C) were optically optimized and studied. In Batch 2, the effective lifetime of "lifetime samples" with 1-2 nm PECVD SiO x \30 nm PECVD (p + ) mc-Si:H\70 nm PECVD SiN x :H was measured. In Batch 3, the passivation of "lifetime samples" with 1-2 nm wetchemical SiO x \30 nm PECVD (p + ) mc-Si:H\70 nm PECVD SiN x :H was studied as well. Batch 4 was a reference passivation batch, in order to evaluate the highest passivation that can currently be reached on our wafers, by depositing a stack of 10 nm (i) a-Si:H\60 nm (n + ) a-Si:H followed by a 220°C annealing step for 10 min.

Characterization
The optical properties of the deposited layers were measured by spectroscopic ellipsometry (SE) with a Horiba Jobin Yvon Uvisel 2 ellipsometer. The data were processed with the DeltaPsi2© software.
The X-ray Photoelectron Spectroscopy (XPS) analyses were carried out with a Thermo Fischer K-Alpha + spectrometer using a monochromatic Al-ka source at 1486.6 eV. The in-depth composition and chemical environments were obtained by sequential Ar + sputtering (1000 eV, 30 s). The XPS spot size was 400 mm for a depth probed in the range of 10 nm. High resolution spectra were acquired using a 20 eV pass energy. Data were processed using the Thermo Avantage© software.
Images of the surface of the samples were acquired with an OLS5000 confocal microscope (Olympus). Lifetimes of the symmetric samples were measured by Quasi Steady-State Photoconductance using a WCT-120 (Sinton Instruments). Photoluminescence (PL) images calibrated in lifetime were acquired with an LIS-R2 (BT Imaging).

PECVD process
We developed a process for depositing SiO x by PECVD at 175°C (Batch 1). In order to supply the required oxygen amount, we increased the r = CO 2 /SiH 4 gas flow rates ratio. The optical properties of these films were measured by SE, and fitted with Tauc-Lorentz model [7]. For r = 10 we got a material with n(633 nm) = 1.6 and k(400 nm) = 0.007.
In standard passivating contact fabrication, a hydrogenated amorphous silicon (a-Si:H) layer is deposited, and then annealed for a long time at high temperature (usually 850°C for 30 min or more [5,[8][9][10]). This can lead to the formation of blisters. The aim of this work being to spend a low thermal budget, this annealing step was skipped. A single firing step, however, leads to even higher stress, resulting in an easier formation of blisters. One way to tackle this issue was to dilute SiH 4 into H 2 [10,11]. We deposited 1-2 nm of PECVD SiO x (30 s deposition), and subsequently deposited the boron doped silicon layer on top of it. Doing so, we varied the SiH 4 flow rate, and consequently its dilution into hydrogen. The samples were then subject to a firing step (850°C for a few seconds). The confocal images of the surface are shown in Figure 1. It can be seen that at lower R = H 2 /SiH 4 flow rate ratio (R = 50), a lot of blisters form, whereas at R = 125, none can be seen. The thicknesses of the layers are respectively, for R = 50/ 63/83/125: 38/33/26/24 nm, measured by ellipsometry in the layers that are shown in Figure 1. Experiments were carried out with adapted layer thicknesses (35/37/35/ 37 nm) and the same trend is obtained, with blisters appearing for the first 3 samples, and no blister for R = 125.
The optical properties of these four samples were measured by SE before annealing, and models have been made in order to fit them as a stack of a SiO x layer with fixed optical properties À known by SE measurements from the SiO x optimization step À and an effective medium layer composed of a mixture of a-Si:H, voids and mc-Si:H on top of it (Bruggeman model [12]). Figure 2 shows the crystalline fraction of the silicon layer (fraction of the material being fitted as small-grain c-Si material), and the fitted thickness of the underlying oxide layer. The crystalline fraction increased when decreasing the silane flow rate. Surprisingly, the thickness of the oxide layer also seemed to decrease. In order to investigate this phenomenon, an XPS analysis was carried out on the samples deposited with R = 50 and R = 125 flow rate ratios.  Contrarily to what was estimated by SE, for sample with SiH 4 /H 2 = 125, this profile shows that the oxide layer is still present in-between the c-Si and the mc-Si:H layer. An oxygen concentration bump is clearly visible, with a maximum of the oxygen content corresponding to the moment when the surface of the silicon oxide layer is reached. Indeed, since depth resolution is limited by the approximate 10 nm escape depth of the photoelectrons, the oxygen starts being detected before the interface is physically reached by sputtering and then starts decreasing afterward, while the Si content conversely rises. Figure 4a shows the Si2p core levels measured at the surface of the buried oxide layer samples with a-Si:H (R = 50) and mc-Si (R = 125) as silicon layer. The reference spectrum obtained on a 1-2 nm of SiO x deposited by PECVD on a silicon wafer previously cleaned by HF is presented as a comparison. The intensity of the peak situated at 98.8 eV corresponding to the Si-Si bonds is the same for all the spectra. Since it is related to the collection of the photoelectrons emitted by the c-Si wafer underneath the oxide, and that the intensity decreases with the thickness of oxide on top of it, we can assess that there is no apparent etching of the SiO x layers. However, it can be seen that the Si-O contributions at higher binding energy are notably modified. The well-defined and roughly symmetric characteristic feature around 103.0 eV obtained for the reference PECVD SiO x , is modified indicating changes in the oxide network and the presence of a set of suboxides in relation with the tail like shape of the left part of the Si2p peak. This is an important piece of information since it   means that in both studied conditions the deposition of the silicon layer changes significantly the oxide layer chemistry. Figure 4b shows the corresponding O1s photopeaks. It can be seen that the overall oxygen content of the encapsulated layers has significantly decreased, in agreement with the presence of suboxides. A possible explanation for the oxygen loss after silicon deposition may be an etching phenomenon by the hydrogen plasma operated during the (p) mc-Si:H deposition step. To sum up, the deposition of the silicon layer on top of our SiO x layer grown by PECVD does not remove it nor reduce its thickness, but it modifies its chemistry, leading to oxygen removal, and changes in the oxidation degree. However, no major difference could be observed between the two samples studied (a-Si:H with R = 50 and mc-Si with R = 125), thus questioning the accuracy of the SE model for such thin buried layers.

Passivation of FZ DSP wafers
In Tables 2 and 3 Figure 5. Locally, the passivation achieved is significantly higher than the average 909 ms, reaching values up to 1.3 ms.  The samples have been submitted to a firing step. The passivation was severely damaged (5 ms, 570 mV). This was an expected behavior in the case of no further hydrogenation step. Indeed, Lehmann et al. have recently shown that in the case of fired passivated contacts, a subsequent hydrogenation step is necessary in order to achieve high passivation quality [13]. Further investigations need to be carried out on the capping layer in order to hinder the hydrogen effusion during this step.

Cz vs. mono-cast textured wafers
For industrial integration, it is of major importance to deposit the passivating contacts on industrially relevant substrates, such as textured Cz or mono-cast silicon wafers. The passivation provided by passivated contacts with wet SiO x is also compared with the one provided by amorphous silicon ((i) a-Si:H\(n + ) a-Si:H stack) as reported in Table 4. No difference is observed between mono-cast and Cz wafers as far as iVoc is concerned, meaning that the integration of passivating contacts on mono-cast wafers is definitely worth being investigated. It is broadly known that textured wafers are harder to passivate than chemically polished wafers, mostly because of increased surface area and a greater number of crystallographic imperfections [14]. As a consequence, the process still needs to be optimized to reduce the difference between passivating contacts and a-Si:H passivation, and the firing step needs to be carried out in order to allow the hydrogen contained in the SiN x :H layer to diffuse and passivate the interface.

Conclusion
In this study we have shown that it is possible to achieve a blister-free passivating contact structure after a single firing step by depositing doped mc-Si:H by PECVD without annealing on top of the oxide layer. It has been demonstrated that this deposition step leads to changes in the buried oxide stoichiometry, with evident oxygen loss, causing conversion into suboxide phases and probable oxide network modification. 693 mV of iVoc and 930 ms of lifetime were reached on a p-type FZ wafer with a simple stack of wet-SiO x \(p + ) mc-Si:H\SiN x :H in the as-deposited state, with no annealing step. The comparable passivation between Cz and Monocast wafers showed that it is of interest to keep studying the integration of passivating contacts on this kind of wafers.