Open Access

Atomic-layer-deposited (ALD) aluminum oxide (Al2 O3 ) has recently demonstrated an excellent surface passivation for both n - and p -type c-Si solar cells thanks to the presence of high negative fixed charges (Q f  ~ 1012 −1013 cm-2 ) in combination with a low density of interface states (D it ). This paper investigates the passivation quality of thin (15 nm) Al2 O3 films deposited by two different techniques: plasma-enhanced atomic layer deposition (PE-ALD) and Thermal atomic layer deposition (T -ALD). Other dielectric materials taken into account for comparison include: thermally-grown silicon dioxide (SiO2 ) (20 nm), SiO2 (20 nm) deposited by plasma-enhanced chemical vapour deposition (PECVD) and hydrogenated amorphous silicon nitride (a-SiNx :H) (20 nm) also deposited by PECVD. With the above-mentioned dielectric layers, Metal Insulator Semiconductor (MIS) capacitors were fabricated for Q f and D it extraction through Capacitance-Voltage-Conductance (C -V -G ) measurements. In addition, lifetime measurements were carried out to evaluate the effective surface recombination velocity (SRV). The influence of extracted C -V -G parameters (Q f ,D it ) on the injection dependent lifetime measurements τ (Δn ), and the dominant passivation mechanism involved have been discussed. Furthermore we have also studied the influence of the SiO2 interfacial layer thickness between the Al2 O3 and silicon surface on the field-effect passivation mechanism. It is shown that the field effect passivation in accumulation mode is more predominant when compared to surface defect passivation.


Introduction
It is well known that the thermal silicon oxide (SiO 2 ) is a very good surface passivation material for crystalline Si (c-Si).However, the formation of thermal SiO 2 requires a high-temperature process (>1000 • C) which does not only increase the processing cost, but may also degrade the quality of the silicon wafer.Therefore, passivation materials that can be deposited at low temperatures are required.Hydrogenated amorphous silicon nitride (a-SiNx:H) obtained by plasma-enhanced chemical vapour deposition (PECVD) is commonly used as front surface emitter passivation and anti-reflection coating (ARC) for both n-and p-type low-resistivity c-Si solar cells.This material can be deposited by PECVD at low temperatures i.e. less than 300 • C. Surface passivation of c-Si solar cell with atomic layer deposited (ALD) aluminum oxide (Al 2 O 3 ) is a good candidate for both p-and n-type surfaces as well as highlydoped p-type emitters, due to its very high built-in negative fixed charge density (Q f ∼ 10 12 −10 13 cm −2 ), low interface state density (D it 10 11 eV −1 cm −2 ) and low surface recombination velocity (SRV 5 cm s −1 ).Best reported conditions were obtained by plasma-ALD process a e-mail: Raja.Kotipalli@uclouvain.be with film thickness ranging from 5 to 30 nm at deposition temperatures between 150−250 • C followed by an annealing step in nitrogen or forming gas atmosphere at 400 • C on low-resistivity Si wafers [1][2][3][4][5][6].
To understand the involved surface passivation mechanism, Girisch et al. [7] introduced an extended Shockley-Read-Hall (SRH) formalism to model the surface recombination mechanism, which included the effects of band bending due to fixed insulator charges (Q f ) and charged interface states (D it = qN it ) over the entire band gap.By assuming the case of single defect level at mid-gap, the surface recombination rate (U s ) can be written as an energy independent quantity [3,[7][8][9][10].
U s ∼ = n s p s ns Sp + ps Sn (1) where: n s and p s are the surface concentrations of electrons and holes respectively.-S n S p are the surface recombination velocity parameters given by S n = σ n v th N it , S p = σ p v th N it .σ n , σ p cross-section of electrons and holes respectively.v th being the thermal velocity.
From the above equation ( 1) one can estimate the surface recombination velocity (SRV) at a particular injection level given by the excess carrier density(Δn).

SRV =
U s Δn . ( Surface recombination rate (U s ), can be reduced by altering two fundamental mechanisms: (i) Reducing the interface state densities D it (i.e.Chemical passivation) The D it is dependent on material and chemical processes used in the fabrication of the solar cell.For example its reduction can be realized by diffusing hydrogen into the silicon/dielectric interface to replace the dangling bond defects.(ii) Reducing the surface concentration of minority carriers (i.e.Field-effect passivation) The surface recombination rate (U s ) can be reduced by decreasing one of two carrier concentrations at the silicon surface typically, the minority carrier concentration.This can be achieved by the fixed charges existing in the dielectric layer.Specifically, these charges creates a built-in electric field which shields the minority carrier to be recombined at the surface by driving the device into accumulation or inversion modes depending on the charge sign (positive or negative) and the chosen substrate type [3,8].
In this article we study the surface passivation mechanism induced by negative fixed charges in Al 2 O 3 films along with other fixed positive charge dielectrics.After a general introduction about the surface passivation mechanism, we describe the metal insulator semiconductor (MIS) capacitor device fabrication, lifetime sample preparations and electrical characterization techniques we used to extract the main parameters involved in the quality of the passivation, i.e.Q f , D it and SRV in Section 2. Section 3 reports the experimental results of all the considered dielectrics.A discussion on the influence of films characteristics on the nature of interface passivation will be held.Subsequently, the impact of interfacial SiO 2 layer on the field-effect passivation will be addressed in Section 4. Finally, in Section 5, conclusions are drawn from our Al 2 O 3 passivation study of Si surfaces.

Samples fabrication and characterization techniques
It clearly appears from equations (1)−(2) that insight knowledge about the density of interface states (D it ) and surface concentrations of carrier n s , p s (depends on Q f ) gives in-depth information about the passivation quality of dielectric films.To extract these values we have considered MIS capacitors as test vehicle.

Dielectric film deposition
Thermal SiO 2 was grown up to a thickness of 20 nm at 1050 • C in an ultra-dry oxygen atmosphere using vertical furnace from Koyo Thermo Systems for a duration of 10 min.
For PECVD SiO 2 20 nm-thick layers were deposited in a parallel plate reactor from Oxford Plasmalab system 100.The deposition parameters used during the film growth were: chamber pressure 0.8 Torr, deposition temperature 300 • C, gas flow: SiH 4 -500 sccm, N 2 O-20 sccm and O 2 -5 sccm.PECVD a-SiNx:H 20 nm-thick layers were also deposited using the same Plasmalab system 100.In this case, Silane (SiH 4 ) and ammonia (NH 3 ) were used as reactive gases in the chamber.During the deposition, SiH 4 was diluted to 5% in pure nitrogen.The deposition parameters used for the film growth were: chamber pressure 0.8 Torr, deposition temperature 300 • C, radio frequency (RF) power 20 W, plasma frequency 13.56 MHz, gas flow: NH 3 -1.8sccm, SiH 4 -10 sccm, and N 2 -700 sccm.
In the case of Al 2 O 3 , 15 nm-thick layers were deposited in a Fiji F200 ALD system from Cambridge NanoTech by thermal atomic layer deposition T -ALD and plasma enhanced atomic layer deposition PE-ALD.In both cases, trimethylaluminum precursor (TMA) from Sigma-Aldrich was used as aluminum source.Depositions were performed at 250 • C for both T -ALD and PE-ALD with argon as a carrier gas.Purge after precursor pulse is mandatory to avoid chemical vapor deposition.Before the deposition, all the samples were kept in the deposition chamber for 1800 s for pumping away H 2 O or O 2 .Each precursor flows separately through the deposition chamber.TMA pulse duration and purge time were 0.06 s and 10 s respectively for T -ALD and PE-ALD depositions.For T -ALD the precursor was de-ionized water while for PE-ALD, oxygen flow is used instead of water pulse.The flow was 30 sccm and plasma power was 300 W. The pulse duration and purge time of the plasma were 20 s and 5 s, respectively.The growth rates were observed to be 1 Å per cycle for both PE-ALD and T -ALD [11][12][13][14][15].

Device fabrication and C-V-G measurements
MIS capacitors were fabricated on p-type, Cz 100 silicon wafers with a resistivity of (1−3) Ω cm as illustrated in (Fig. 1).
Before the deposition of the dielectric layers, all the wafers were cleaned using Piranha solution (3:1:H 2 SO 4 :H 2 O 2 , for a duration of 20 min at 120 • C).After the Piranha cleaning the wafers were dipped in dilute HF solution (1:50:HF:DI water) at room temperature to remove the native oxide.The etching of native oxide layer is confirmed by the appearance of hydrophobic Si surface.Next, dielectric layers described in the above Section 2.1 were grown or deposited.Then, gate electrodes with an active area of 1 mm 2 were patterned on the front side of the samples using an image reversal lithography step (i.e.resist coating, pre-bake, image exposure with mask, post-exposure bake, flood exposure and development).A 300 nm Al layer was evaporated on the front side of the samples followed by a lift-off in acetone.After front side device fabrication, full-area aluminum back contact (300 nm) is evaporated on the backside of the wafers.Finally, all the samples were annealed in forming gas (N 2 /H 2 : 90/10%) ambient at 432 • C for 30 min.
Capacitance-voltage-conductance (C-V -G) measurements were performed with Agilent B1500A Semiconductor device analyzer at different frequencies ranging from 1 kHz to 1 MHz.To confidently extract the interface trap charge densities (D it ) at the silicon/dielectric interface we used different available extraction methods namely: High-Low frequency method, Terman method and Conductance method.The fixed charge density (Q f ) in the dielectric was estimated from the flat-band voltage of the low-frequency C-V curve [16][17][18][19][20][21].

Sample preparation for lifetime measurements
In our experiments, to emphasize the electronic properties of the dielectrics, we have chosen p-type, Boron doped, 200 μm thick double-side polished, 111 , Float zone (FZ ) silicon wafers in order to neglect the bulk lifetime in SRV extractions.A choose of high resistivity >5000 Ω cm wafers in particular is to avoid the bandgap defects induced by impurity dopants which acts like an effective recombination centers for SRH.Since the dopant impurity concentration sets the Fermi level, lowresistivity materials are more sensitive to these defects than high-resistivity material.So the dominant recombination in these samples is only due to Auger and radiative mechanisms.Lifetime measurements were performed using Sinton WCT-120 lifetime tester in both quasi steady state and transient modes.The different dielectric layers under consideration were symmetrically deposited on both sides of the wafers, followed by a forming gas annealing at 432 • C for 30 min to activate the passivation mechanism [22,23].

Passivation analysis using different dielectrics
The C-V characteristics of MOS capacitors measured at 10 kHz for the different considered dielectrics are shown in Figure 2. The flat-band voltage (V fb ) of the lowfrequency C-V curve allows calculation of the density and the polarity of charges present in the dielectric film from the following equation:  where Φ ms = −0.96V is the difference between the aluminum and silicon work functions.The flat-band voltage (V fb ) of the MOS capacitors with the PECVD Si 3 N 4 , PECVD SiO 2 and thermal SiO 2 films is negative (i.e.lower than Φ ms ), meaning these films contain fixed positive charges (Q f ).For the T -ALD and PE-ALD Al 2 O 3 films, the V fb is positive and Q f is negative [16][17][18].

Interface states densities (D it ) extraction methodology
The extraction of interface state density (D it ) using only one method may suffer from parasitic effects such as high leakage currents through the dielectrics (thin) films, series resistance from the measurement setup and frequency-dispersion related problems in accumulation region.These parasitic effects will definitively alter the measured capacitance-conductance (C-G) values, which will in turn affect the interpreted D it by up to an order of magnitude.To minimize the influence of these effects on the extracted interface states densities (D it ), all the measured C-V -G curves were first corrected for parasitic free C-V -G curves using "dual-frequency five-element small-signal circuit model " as shown in (Fig. 3) [19][20][21]24].
To assure that the extracted D it values are correctly estimated over the entire band gap and not affected by parasitic effects, we extract the D it using three different methods described below.
-Figure 4b shows the D it extraction using high-low frequency method, which compares the quasi-static C-V (QSCV) curve with a high frequency (1 MHz) C-V curve.In the QSCV measurement the interface traps are assumed to follow the slowly varying dc bias, contributing to interface trap charge capacitance (C it ).
On the contrary, in the high-frequency C-V measurement the interface traps cannot follow the applied high-frequency ac signal, making the interface trap charge capacitance be zero (C it = 0).The value of C it can then be estimated by comparing the difference in capacitance between quasi-static and high frequency C-V curves from depletion -inversion regions (i.e.yielding D it for mid-gap potentials) [20,21].-Figure 4c illustrates the D it extraction using Terman method, which is based on the stretch-out phenomenon in the experimental high-frequency C-V curve compared to theoretically simulated high-frequency C-V curve (i.e.ideal) with no interface traps.From the ideal C-V curve finding the surface potential (ϕ s ) for a given capacitance value in the depletion regime, and interpolating it on the experimental gate voltage (V G ) curve gives us the (ϕ s −V G ) relation.Repeating this for other points from accumulation to inversion regimes results in a (ϕ s −V G ) curve.This ϕ s versus V G curve is stretched-out when compared to theoretical curve without D it , this stretch-out yields the information about the interface state densities [17,19].-Figure 4d represents the D it extraction using conductance method.This method is based on measuring the equivalent parallel conductance per unit area (Gp) as a function of bias voltage and frequency (ω).This equivalent parallel conductance represents the energy loss caused by capture and emission of carriers from the interface traps when gate bias is swept from accumulation to inversion regimes.Plotting ( Gp ω ) with respect to frequencies in the depletion range of gate voltages yields the maximum of energy loss mechanism due to interface states.This peak (maximum energy loss) value of ( Gp ω ) max gives direct information on D it [16][17][18].[16,25,26].

Carrier lifetime measurements
To enable carrier lifetime testing, the respective dielectric layers were deposited on both sides of a wafer to maintain symmetrical structures.Supporting the above extracted C-V -G parameters (Q f , D it ), minority carrier lifetime measurements (Fig. 5) show that thermally grown SiO 2 leads to a good passivation quality independent of injection level, mainly due to very low D it [8,9].The quality of surface passivation is indeed also examined by effective surface recombination velocity (S eff ) calculated from the lifetime measurements.A common typical injection point of Δn = 5×10 15 cm −3 has been chosen for S eff extraction for the comparison of the different dielectrics [8,11,12].
where W is the thickness of the substrate.Assuming a very high lifetime, thanks to the use of FZ wafers equation ( 4) can be simplified and the maximum S eff max can be calculated by while the lower limit is the case where no recombination occurs.In reality the value of S lies in-between (0 < S < S effmax ) depending on the chosen injection level (Δn) [8,11,12,27,28].Table 3 presents the surface recombination velocities (SRV) extracted from the lifetime measurements using equation ( 5) for 200 μm thick wafers covered with the different dielectrics.Samples with PE-ALD show the lowest SRV among all other dielectrics considered in this experiment with a value of less than 5 cm s −1 though it presented the highest D it .
Our experimental results have shown that a good silicon surface passivation is achieved with ALD Al 2 O 3 as dielectric film.This is attributed to a high density of negative fixed charges presented in the film, compensating the detrimental role of higher D it .
The source of these negative fixed charges is attributed to the trapped hydroxyl groups in the film due to the deposition process [10,14,15,29].Another possible reason could be the presence of Al vacancies in the Al 2 O 3 film or oxygen interstitials located at the Si/SiO X /Al 2 O 3 interfaces [3,8,9,11,12,30].Al 2 O 3 surface passivation can be described as a combination of both field-effect passivation and chemical passivation.Similar to other dielectrics, Al 2 O 3 also chemically passivates the surface by releasing hydrogen atoms, which diffuse to the Si/dielectric interface to passivate the dangling bond defects.Apart from this, Al 2 O 3 also serves the field-effect passivation mechanism due to its high fixed negative charge density, which is one-two orders of magnitude higher when compared to SiO 2 deposited by PECVD and two orders magnitude higher than thermally-grown SiO 2 (Tab.1).This high amount of negative fixed charges in the overlying dielectric film drives the silicon surface into accumulation mode in case of p-type substrate creating a built-in E-field (electric field) at the surface shielding the minority carriers (here electrons) to recombine at the surface This difference in field passivation significantly relaxes the requirements on the interface defect density (D it ) at the c-Si/Al 2 O 3 interface.Figure 5 clearly shows two separate groups of curves, two lower curves corresponding to SiO 2 -PECVD and Si 3 N 4 -PECVD and three others.The field effect is more effective in the low injection regime, whereas at high injection, while photo-generated excess charges compensate the fixed charges that induced the field effect, and mainly the "chemical passivation" is dominant [3, 4, 8, 9, 11-13, 24, 30-33].
The shape of the τ (Δn) curves (Fig. 5) can reveal information regarding the involved interface passivation mechanism [34].
-From Tables 1 and 2 Thus the difference in lifetimes behavior especially at lower injection range can be solely attributed due to the field passivation.This is mainly induced by fixed charges in dielectrics.Comparing 4 Field effect passivation dependency on interfacial (SiO 2 ) layer thickness Kessels et al. [13] reported that a thin interfacial SiO 2 (∼1−2 nm) layer is formed naturally between Si surface and Al 2 O 3 layer.This thermal SiO 2 (∼1−2 nm) is the only means of chemical passivation at the interface.The thickness of this SiO 2 is too thin to completely passivate the interface states.Another disadvantage of this interfacial oxide is that it may not have the same quality as SiO 2 produced by thermal oxidation of Si.In some experiments we have introduced a stack of SiO 2 /Al 2 O 3 on the Si surface.The main goal of this experiment is to chemically passivate the Si surface by thermally growing SiO 2 and maintains field-effect passivation with negative charges present in Al 2 O 3 .To perform this and investigate trade-offs between concurrent Q f and D it reductions, we have thermally-grown SiO 2 layers with two different thicknesses: 8 and 20 nm [11,13].
An Al 2 O 3 film of 15 nm was deposited on SiO 2 samples using PE-ALD.The deposition was also performed directly on the Si as a reference sample [3, 11-13, 24, 30-33].All these samples were treated in the same way as in the earlier experiments for both C-V -G and lifetime measurements except that the Al 2 O 3 layer deposition was performed at 200 • C.
From SRV results, we observe that the SiO 2 (8 nm)/Al 2 O 3 (15 nm) stack exhibits the lowest SRV values compared to other samples.This can be correlated to negative Q f and low D it extracted (Tab.4) from C-V -G curves (Fig. 6).
As reported by other authors [4,13], the chemical passivation at the interface of Al 2 O 3 /Si occurs during the annealing step, when a very thin interfacial Al x SiO y layer is created in between the two materials.The formation of this layer is not well understood at this time as oxygen and hydrogen seem to play an important role,  but consequences have been demonstrated and shown that electrically active interface traps were reduced.For the reference Al 2 O 3 sample, the flat-band (V fb ) is positive and the density of negative fixed charges (Q f ∼ 8.5 × 10 12 cm −3 ) and the interface defect density (D it ∼ 2.7×10 11 eV −1 cm −2 ) are higher than any other sample in this experiment.However, an SRV of 9 cm s −1 is obtained from lifetime measurements meaning that the field effect passivation is predominant in this sample and slightly relaxes the requirement for lower D it values.
For the sample with SiO 2 (8 nm)/Al 2 O 3 (15 nm) stack, the V fb is negative but still exhibits negative fixed charges, however, twenty times lower than in the reference sample (only Al 2 O 3 ).It is important to notice that the D it also reduces by four times due to the presence of thermal-SiO 2 layer, which reduces the defects at the interface and also the field induced by Al 2 O 3 layer.This reduction of the effective field when using an SiO 2 layer can be explained by the fact that the charge centroid is driven away from the silicon surface with increasing SiO 2 thickness, as well as by the contribution of fixed positive charges in SiO 2 layer resulting in overall reduction of net effective negative charge density.However, the trade-off between Q f and D it obtained in these conditions leads to a much better effective lifetime at all injection levels.The difference is larger at low injection level where the field effect is the more efficient showing that 8 nm-SiO 2 does not shield too much the Al 2 O 3 charges [3, 4, 8, 9, 11-13, 24, 27, 28, 30-33].
In the case of thicker SiO 2 layer (20 nm), the "chemical interface" between Si and SiO 2 is the same as thinner SiO 2 (8 nm) layer.We can observe from Figure 7 that the effective lifetime is affected over the complete range of injection level.C-V measurements on this sample confirm that the silicon oxide layer has reduced the interface trap charge density (D it ∼ 2.1 × 10 10 ) and also the fixed charges den- sity (Q f ∼ −1.9×10 11 ).The effective lifetime is even lower than with Al 2 O 3 layer alone and has returned to the values previously obtained for SiO 2 only, meaning that fieldeffect passivation has been completely lost and the only means of passivation is due to chemical-passivation [10].

Conclusion
Electronic properties (Q f , D it ) of different dielectrics were extracted.In addition, parasitic C-V -G corrections were applied to accurately estimate the interface trap charge density.Extracted parameters were discussed and compared with lifetime measurements to understand the passivation mechanisms involved at the interface.
In case of the PE-ALD Al 2 O 3 layer, the extracted fixed charge density is negative and about −5.2 × 10 12 cm −2 , which provides an effective field-effect passivation for impeding the surface recombination of minority carriers.Interface trap charge density D it has been calculated and is found to be about 3 × 10 11 cm −2 eV −1 as a mean value in the depletion gate voltage range.Such high negative fixed charge density resulted in surface recombination velocity less than 3 cm/s due to formation of accumulation regime at the silicon surface.
We have demonstrated the dependency of field-effect passivation on the thickness of SiO 2 interfacial layer.From the C-V -G parameter extractions and lifetime measurements we concluded that an optimal thickness of SiO 2 (here 8 nm) reduces the interface state densities while still maintaining field-effect passivation.Thick SiO 2 layer reduces the net negative charge effect in the overall dielectric and may lead to a loss of the field-effect passivation.
We have observed that accumulation mode leads to better passivation than inversion mode.In our experiments, high negative fixed charges dielectrics were less sensitive to interface trap defects and exhibits better passivation behavior over all injection range.More generally, for all dielectrics, field-effect passivation mainly drives surface recombination at low injection, as chemical passivation is more predominant at higher level.

Fig. 2 .
Fig. 2. Normalized C-V Characteristics of different dielectrics at 10 kHz to extract the fixed charge density (Q f ).

Fig. 3 .
Fig.3.Typical quasi-static (QSCV) and high-frequency (HF) C-V curves for a MIS capacitor with SiO2 dielectric.The HF curve is also represented after parasitic free (frequencydispersion related problems in accumulation gate voltages) correction using "dual-frequency five-element small-signal circuit model".

Tables 1 and 2
summarize extracted results from C-V measurements on MIS capacitors: oxide capacitance in accumulation (C ox ), flat band voltage (V fb ), fixed charge density (Q f ) and interface trap charge density (D it ) using different methods.The range of Q f and D it values are estimated considering variations of oxide thickness ±(0.1−2) nm and substrate resistivity (1−3) Ω cm.

Table 1
highlights that the PECVD Si 3 N 4 layer has a high density of positive charge ∼4.2 × 10 12 cm −2 compared to other dielectrics.Al 2 O 3 dielectric films exhibit

Table 2 .
Extracted interface state density (Dit) from C-V measurements.
negative fixed charge densities as high as −5.3×1012cm −2 and −2.3 × 10 12 cm −2 when deposited by PE-ALD and T -ALD respectively.In our experiments, Al 2 O 3 deposited by PE-ALD exhibits more negative charges than T -ALD process.Table2summarizes the extracted D it values using different methods.The relative differences can be related to the various specificities and sensitivity ranges of the different extraction methodologies, but also to the fact that the D it values extracted from each method may not be extracted at the same gate voltage (i.e.depletion point).In addition, other errors could be due to nonuniform doping of the substrate, failure to obtain accurate 1 MHz high-frequency curves or inaccurate band bending during low-frequency measurements, which may affect the estimations.The D it orders of magnitudes are correctly estimated and can be used as figures of merit to compare the different dielectrics.However, the D it values extracted using conductance method on Al 2 O 3 PE-ALD, T -ALD samples exhibit slightly higher values due to the asymmetry of the capture cross-sections σ n /σ p in these dielectrics, influencing the extractions using this method
in combination with a high density of positive Q f ∼ 4 × 10 12 cm −2 .Even if the net charges is at the same level as Al 2 O 3 , the field effect passivation due to positively charged layers is less effective on p-type substrates resulting in a lower passivation quality.Accumulation mode caused by negative charges is more efficient than inversion caused by positive charges on p-type surfaces.This difference is probably due to the depletion layer beneath the inversion layer where n s and p s concentrations are at the same level.-Lowfixed positive charges in PECVD-SiO 2 and thermal dielectric layers leads to weak inversion or depletion mode for which the resulting field effect is not efficient.SiO 2 -thermal lifetime curves exhibit almost injection independent behavior meaning that the dominant passivation mechanism involved at the interface is the chemical passivation, i.e. lowest D it ∼ 2 × 10 10 cm −2 eV −1 .